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2007-07-25: SPECfp_base2006

Category: General
Posted by: afeldstein
SPECfp2006 results

2007-07-19: Life's Too Short

Category: General
Posted by: afeldstein
Something bad happened this week. Or maybe it happened in March.

I've been using LinkedIn to help build professional relationships for mutual benefit. I also happen to be for hire. In March, I successfully used my network to get introduced to someone at one of the companies on my short list. (If you know me well, then you know that it is a very short list and you can recite it.) He called me and we had what I thought was an interesting and friendly conversation. He gave me a green light to invite him to connect on LinkedIn. So I did.

Four months later he still hadn't accepted my invitation. There are all kinds of LinkedIn users, so it's not unusual for someone to not notice for several months that he/she has been invited.

This week, as I'm attempting to strengthen my relationships with that company and leverage my specialization in a particular instruction set architecture with mixed results, I decided to give him a call. I reached his voice mail and left him a short and pleasant message, reminding him that I would like to connect on LinkedIn. Keep in mind that this is my first contact with him in four months, hardly to be considered nagging.

The next day I received the following email from him with the subject, "Please leave me alone":

Feldstein,

I received you phone call last night. I did not forget about your invitation, it was ignored. I initially was glad to help you but after talking with you I do not feel comfortable having you in my network. The damage is already done with me and would recommend that you careful when you are dealing with others. I know that I am not the first person who you turned off.

Please do not attempt to contact me. This issue is closed.


He sent this from his corporate email address and sent a copy to a friend of mine at the same company, also to his corporate email address!

Am I stumbling through life pissing people off without even realizing it? I'm really a nice guy. I want most to apply my considerable talent and join the cause that any one of the companies on my short list represents. I also want to learn from the capable people around me and enhance their careers through my presence and actions. The focus is unselfishly on the product and things tend to fall into place when we do that. It's hard to believe that I would be so misunderstood (or underestimated).

The email above is not particularly helpful, except perhaps to point out that I need to be more perceptive in interpersonal relationships. I have absolutely no idea what I did to turn this person off. Feedback would be constructive. I am very thick-skinned. I can take it and I invite it, from all of you.

Life is too short to bad mouth this person for ...

I don't need to finish that sentence. Just know that I want to make people happy. And there's no way that I'm going to cross that company off my list.
Category: General
Posted by: afeldstein
Do you remember when I said that "any SPARC-V9 implementation, including the OpenSPARC T1 processor, can be described by a functional/structural model in JHDL" and that "FSS should be able to verify OpenSPARC T1"? In fact, one of the goals of FSS is that it be able to verify any microprocessor that tries to implement SPARC-V9. That is what the Feldstein SPARC-V9 Simulator is for.

Before those of you not interested in FSS stop reading, let me point out that most of my recent work in this area benefits anyone using Icarus Verilog for OpenSPARC T1 synthesis. The work is potentially useful even to those who use Icarus Verilog for synthesis of designs other than OpenSPARC.

The problem with Icarus Verilog has been latch synthesis. See "Asynchronous if statement is missing the else clause." for details. Cosmic Horizon has been contributing to Icarus Verilog to remove this limitation.

On 2007-05-20, I submitted my first patch to Steve Williams, owner of the Icarus Verilog project, explaining that with this patch "Icarus Verilog can recognize that a latch is inferred, instantiate a NetLatch object, and connect it to the circuit".

On 2007-06-23, I submitted a second patch, which "takes us to the point where it is revealed that tgt-vvp needs some work". Cosmic Horizon's interest is solely in the fnf target, so I'm going to leave the vvp (Verilog simulator) work to others.

As Steve explained on 2007-04-13, "Synthesis is still pretty much relegated to the 0.8 branch, and will be that way for a while yet. I've got a variety of BIG simulation tasks that are taking priority." And that's where my latch synthesis patches have been committed, the "v0_8-branch" of Steve's Git repository. Access that repository with:

git clone git://icarus.com/~steve-icarus/verilog

Or you can wait until Steve merges synthesis with the trunk and releases an Icarus Verilog version with my improvements. Git, by the way, is a revision control application available here.

There is likely more work to be done on the common Icarus Verilog code to get good FNF. If so, you should see another Icarus Verilog contribution from me in the future.

At this point, those not interested in automated translation of Verilog RTL to other hardware description languages and those not interested in FSS can stop reading.

I mentioned before Tom Hawkins's "path from Verilog to ... JHDL". It is a path that passes through Free Netlist Format (FNF). The Icarus Verilog FNF generator included with Confluence 0.10.6 is an essential piece. On 2007-05-12, I saw Tom's message that "Confluence is no longer in development." Well, the Icarus Verilog FNF generator lives on with Cosmic Horizon and I will redistribute it if necessary. I have already made necessary changes to the Icarus Verilog FNF generator locally.

As I have said before, "In order for FSS to be useful for verification of a user-supplied SPARC-V9 design, that design must be modeled in JHDL." You, the potential FSS users may already have a Verilog RTL design (e.g. OpenSPARC T1), in which case it is unlikely that you would spend much time or money on its translation to JHDL just to be able to try FSS. For you, the translation should be automatic and free.