Finally this month, there is a published POWER5+ result for SPECfp2006, and it isn't pretty. The baseline result of 12.2 compares poorly with the Dual-Core Intel Itanium 2 9050 result of 17.3. That's a speedup of 1.42 for customers switching to Itanium. As long as Itanium is in the number one spot, only a fool would ignore it. I can assure you that the decision-makers at IBM, Sun, and Fujitsu are not fools. As for some of the folks over at the INQUIRER, you know who you are.
Please scroll down for comparison table.
Incisive Design Team family | Feldstein SPARC-V9 Simulator (FSS) |
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RTL block-level designs | |
RTL chip-level designs | structural chip-level designs |
standard languages | JHDL |
simulation acceleration | would benefit from Java acceleration |
testbench automation | automated verification |
Assertion-Based Verification (ABV) | Java assert statement (to programmatically implement preconditions and postconditions or to verify any other intermediate states that help you ensure your code is working correctly) |
Incisive Design Team Simulator Utilizes single-kernel architecture for efficient verification of models and testbenches based on Verilog®, System Verilog, VHDL, SystemC®, Property Specification Language (PSL), and Open Verification Library (OVL). HDL analysis, integrated code coverage and powerful interactive debug complete this simulation solution.
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Incisive Design Team Manager (automates and guides the verification process and then analyzes data, from planning to closure) |
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not even designed specifically to verify microprocessor designs (very wide scope) | designed specifically to verify SPARC-V9 implementations (very narrow scope) |
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Incisive Design Team Formal Verifier (provides a formal means of verifying RTL functional correctness with assertions, without the need of testbench simulation) | |
Incisive Design Team Xtreme® series (accelerators/emulators) | would benefit from Java acceleration |
expensive | free* |
Sun Solaris, HP-UX, Linux | will execute on any computer platform that supports Java |
comprehensive plan-to-closure methodology | |
System Verilog testbench | JHDL testbench |
* A feature-limited free version (Requirement 1.3) will always be available, and is being developed far beyond its current capability. In the future, development will be forked, and a full-featured version (Requirement 1.4) will be sold for the price that it commands.